1. Field of the Invention
The present invention relates to semiconductor devices and methods for fabricating same and, more particularly, to a semiconductor device in which a junction termination extension region is utilized to increase the breakdown voltage of the device and to a process for fabricating a semiconductor device including a junction termination extension region.
2. Description of the Prior Art
The maximum reverse voltage that a semiconductor device formed with a P-N junction can withstand is limited by the breakdown voltage of the reverse-blocking junction. The actual breakdown voltage of the junction normally falls short of the breakdown voltage which may ideally be achieved. Such a blocking junction may comprise, for example, a P-N junction of a thyristor, a bipolar transistor, an insulated-gate transistor, or a corresponding junction in a metal-oxide-semiconductor field-effect transistor. Avalanche breakdown occurs in such a device at a voltage substantially less than the ideal breakdown voltage because excessively high electric fields are present at certain locations in the device under reverse bias, i.e., certain "high field points". A high field point of a blocking junction under reverse bias usually occurs slightly above the metallurgical junction along a region of curvature, such as that at the end of the junction.
Semiconductor devices of the prior art utilize various structures and methods to achieve an increase in the breakdown voltage of a P-N junction. For example, junction termination extension (JTE) regions are utilized near terminated portions of the P-N junction. In general, a JTE region may be considered as a more lightly doped extension of a heavily doped semiconductor region that adjoins a lightly doped semiconductor region to form the foregoing P-N junction. The principal function of the JTE region is to reduce the high concentration of electric fields that would otherwise exist in the vicinity of the terminated portion of the P-N junction, and especially at the high field points, by laterally extending the blocking junction.
A multiple-zone JTE region and novel fabrication process are described in U.S. Pat. No. 4,648,174, issued to V.A.K. Temple et al. and assigned to the same assignee as the present invention, the entirety of which is incorporated herein by reference. As described therein, a single mask is used to form the multiple-zone JTE region, with the mask having different patterns of openings in different portions thereof. The method described includes forming the single multiple-zone JTE mask on the semiconductor device, and then using the mask to produce the JTE region by implanting and diffusing the JTE dopant in the device. Subsequent to formation of the JTE, a blocking junction mask is formed on the semiconductor device and the blocking junction material is then implanted and diffused. Although more efficient than other prior art JTE fabrication processes, one drawback to this approach, and to all other JTE formation processes, is the difficulty inherent in diffusing the less concentrated JTE implants near the high field points within the more heavily doped region defining the blocking junction. Typically, 30-40 hours at 1150.degree. C. are required for a successful JTE diffusion. If other junctions have been created in the device prior to the JTE fabrication step, they will also be diffused during the JTE drive, sometimes causing deleterious effects.
Another approach to increasing actual breakdown voltage of the P-N junction is to incorporate a low graded junction within the heavily doped region defining the blocking junction. Such an approach is described in detail in an article by R. Stengl and U. Gosele, entitled "Variation of Lateral Doping -- A New Concept to Avoid High voltage Breakdown of Planar Junctions", 1985 International Electron Devices Meeting, pp. 154-157. With this technique, a continuous lateral doping gradient is achieved by laterally decreasing the diameter of holes in the implantation mask proximate termination of the reverse-blocking junction. The laterally decreasing diameter holes in the implantation mask act as sources for a drive-in diffusion after implantation. In this process, the heavily doped region defining the blocking junction, including the laterally low graded region adjacent thereto, is simultaneously doped and diffused. Although somewhat less time consuming than the single, multiple zone mask JTE creation process, a significant drawback to this low graded junction approach is the lack of design flexibility inherent in fabricating such a graded junction simultaneous with the heavily doped blocking junction region. Further, with this approach consistent attainment of voltages near ideal breakdown is often impossible because of the difficult nature of the process to implement. For example, the implant concentration for the heavily doped region is typically one or two orders of magnitude greater than that desired for the low graded junction and depending upon the implant process used, e.g., photolithography, it may be impossible to define sufficiently small openings in the mask to attain the desired dopant concentrations within the low graded junction.
Thus, known semiconductor device fabrication methods possess disadvantageous processing limitations and/or fail to consistently result in near ideal device breakdown voltages. Accordingly, a semiconductor device and fabrication method utilizing an improved junction termination extension region which is diffused close to the high field point of the blocking junction with no additional diffusion or diffusion time other than that required for the blocking junction is clearly desirable.